NVIDIA opens NVLink Fusion to custom XPUs, targeting 1,152-accelerator AI factories

NVIDIA has published new details on NVLink Fusion, the program that lets hyperscalers and AI-native companies plug custom-built processors (XPUs) into NVIDIA's rack-scale interconnect fabric alongside its own GPUs. The move extends NVIDIA's networking dominance beyond its own silicon and into the growing market for custom AI accelerators.

What's new

NVLink Fusion allows partners to integrate their own CPUs or XPUs into NVIDIA's NVLink domain rather than building a fully separate interconnect stack. According to NVIDIA, the sixth-generation NVLink fabric delivers 3x lower end-to-end latency and 10x higher packet rate than off-the-shelf Ethernet alternatives, while NVLink-C2C chip-to-chip links offer up to 6x better energy efficiency than PCIe.

The current generation supports NVLink domains of up to 72 XPUs — matching the scale of NVIDIA's own GB300 NVL72 rack — with NVIDIA laying out a roadmap toward domains of up to 1,152 accelerators. NVIDIA says its GB300 NVL72 already delivers more than 10x the throughput of the prior-generation B300 in certain inference workloads.

Partners quoted in the announcement frame the appeal as flexibility without giving up NVIDIA's networking stack. Intel's Tim Wilson said NVLink Fusion "gives customers the ability to choose the CPU architecture, the performance level, the software capabilities that best meet their needs," while MediaTek's Vince Hu said it lets customers "deploy their rack-level solution with the NVIDIA GPU, then decouple XPU development at a different pace."

Context

NVLink Fusion was introduced earlier in 2026 as NVIDIA's answer to hyperscalers building their own custom AI silicon — Google's TPUs, Amazon's Trainium, and Microsoft's Maia among them — in an effort to reduce dependence on NVIDIA GPUs. Rather than cede that custom-silicon business entirely, NVIDIA is positioning its interconnect fabric as the connective tissue those chips still need, keeping itself in the revenue path even when a customer's compute isn't an NVIDIA GPU.

Why it matters

The interconnect, not just the chip, has become the real bottleneck and moat in large-scale AI training and inference — clusters of tens of thousands of accelerators live or die on how efficiently they can move data between chips. By opening NVLink to third-party XPUs, NVIDIA is betting it can stay central to AI infrastructure buildouts even as more of the industry diversifies its compute silicon, effectively taxing the custom-chip trend rather than being displaced by it. The jump in roadmap scale, from 72-XPU domains today to a stated path toward 1,152 accelerators, signals how much larger single-fabric AI factories are expected to grow over the next several product cycles.