Cerebras details CS-6 wafer-scale chip with 3D-stacked DRAM at Hot Chips 2026

Cerebras used its Hot Chips 2026 presentation to lay out the next two generations of its wafer-scale AI hardware roadmap, detailing a rack-scale "Nexus" platform architecture and a future CS-6 system that integrates 3D-stacked DRAM directly with its wafer-scale compute, according to a post on the Cerebras blog.

What's new

Cerebras's current generation, the CS-4, runs on a rack-scale platform the company calls Nexus, which "supports three Wafer-Scale Engines, each housed in a modular compute backpack at the rear of the rack." Each backpack bundles one Wafer-Scale Engine (WSE) with its own dedicated power, cooling, and I/O, letting Cerebras iterate on any one subsystem — power delivery, cooling, interconnect — without redesigning the whole rack. Cerebras says this modularity is what lets it commit to a roadmap goal: the architecture is built to "double token-generation speed year over year for the next several years while dramatically improving throughput and efficiency."

Looking further out, Cerebras previewed CS-6, which moves beyond the current wafer-scale SRAM design by adding 3D-stacked DRAM. By "integrating wafer-scale SRAM and compute with 3D-stacked DRAM through ultra-high-bandwidth connections," the company says CS-6 "is designed to dramatically expand memory capacity without sacrificing the locality that makes wafer scale fast" — addressing the main structural limit of wafer-scale chips, where keeping compute and memory on a single wafer maximizes speed but caps how much memory a system can carry.

Ahead of CS-6, Cerebras also detailed CS-5, targeted for 2027, which it says will deliver "up to 10,000 output tokens per second per user on leading open-source models" and, on the largest frontier models, "up to 5,000 output tokens per second per user and 3 million tokens per second per megawatt." On raw interconnect, Cerebras contrasted its current WSE-3T against Nvidia's rack-scale networking, saying a single WSE-3T provides on-wafer fabric bandwidth "more than 200 times the NVL72 rack's scale-up bandwidth," versus the 260 terabytes per second of NVLink bandwidth Nvidia specifies for a full 72-GPU Rubin rack.

Context

Cerebras has spent the past several product cycles arguing that keeping an entire model's weights on-wafer, rather than spreading them across many networked GPUs, is the more efficient path to high-throughput inference — trading Nvidia's massive but power-hungry inter-GPU fabric for a single silicon wafer with everything on it. The tradeoff has always been memory capacity: wafer-scale SRAM is fast but limited in size compared to the HBM stacks on modern GPUs. CS-6's 3D-stacked DRAM is Cerebras's answer to that limit, aiming to substantially grow the memory pool available to a wafer without giving up the locality advantage that makes the architecture fast in the first place.

Why it matters

Inference cost and speed have become one of the most competitive fronts in AI infrastructure as frontier labs push token throughput per dollar down while chasing lower latency for agentic workloads. Cerebras positioning CS-5 around per-user token throughput on "leading open-source models" and per-megawatt efficiency on frontier-scale models is a direct pitch to buyers weighing Cerebras hardware against Nvidia's Rubin generation on a cost-per-token basis rather than raw FLOPs. If CS-6's memory-capacity fix works as described, it would remove the main reason large model deployments have stayed on GPU clusters instead of wafer-scale systems — though as a multi-year-out roadmap item, the real test will be whether Cerebras ships it on the timeline it's describing today.